For a conventional quad flat non-leaded (QFN) semiconductor package with a lead frame, a plurality of leads surrounding a die pad of the lead frame are usually formed with stepped structures or anchoring structures. As shown in FIGS. 1A, 1B and 1C, the stepped structures 41 of the leads 40 in FIG. 1B or the anchoring structures 42 of the leads 40 in FIG. 1C can increase a contact area between an encapsulant 43 and the leads 40 and thus enhance the adhesion therebetween. Such arrangement prevents delamination of the leads 40 or encapsulant 43, and also provides protection for a chip 44 and bonding wires 45 incorporated in the semiconductor package, thereby assuring the structural reliability and electrical quality of the semiconductor package.
However, in accordance with the development of light-weight and small-profile semiconductor products, the conventional lead frame having a limitation on its thickness makes the height of the lead-frame-based semiconductor package not able to be further reduced, and as a result, a carrier-free semiconductor package structure has been produced. The carrier-free semiconductor package does not use the conventional lead frame and thus has a significantly smaller thickness than that of the lead-frame-based package. This overcomes the conventional structural limitation as to failure in reducing the thickness of the semiconductor package.
The above carrier-free semiconductor package advantageously has a reduced thickness, however, it may encounter the problem of delamination of an encapsulant or cracks of bonding wires, etc. due to the absence of the lead frame. For example, referring to FIGS. 2A and 2B showing a semiconductor package disclosed in U.S. Pat. No. 5,830,800, a plurality of electroplated pads 51 are formed on a copper carrier 50 according to predetermined circuitry, wherein each of the electroplated pads 51 comprises Au/Pd/Ni/Pd (gold/palladium/nickel/palladium) plated layers and is approximately 6 μm thick. Then, at least one chip 52 is mounted on the copper carrier 50 and is electrically connected to the electroplated pads 51 via a plurality of bonding wires 53. As shown in FIG. 2B, an encapsulant 54 is formed and encapsulates the chip 52 and the bonding wires 53. Subsequently, the copper carrier 50 is etched off. Finally, a plurality of solder balls 55 are implanted on the electroplated pads 51 to be electrically connected to an external device, such that a singulation process can be performed, and a carrier-free semiconductor package is fabricated.
By comparing the conventional semiconductor package shown in FIG. 1A having the bonding wires 45 connected to the leads 40, and the above semiconductor package of FIGS. 2A and 2B having the bonding wires 53 bonded to the electroplated pads 51, since the thickness of the electroplated pads 51 is merely about 6 μm and much smaller than the thickness (generally up to 200 μm) of the leads 40 in FIG. 1A, the electroplated pads 51 cannot be firmly held by the encapsulant 54 unlike the leads 40 that can be easily held. This thereby causes peel-off of the electroplated pads 51 and detachment of the bonding wires 53. Further due to the insufficient adhesion between the encapsulant 54 and the electroplated pads 51, the electroplated pads 51 may possibly be delaminated from the encapsulant 54 after a surface-mounting process.
Moreover, the topmost Pd layer of the electroplated pad 51 has a much different coefficient of thermal expansion (CTE) from that of the encapsulant 54 and is weakly adhesive to the encapsulant 54. This would cause a delamination problem due to the CTE mismatch and even lead to cracks of the bonding wires 53. Furthermore, when the semiconductor package is mounted on a printed circuit board via the electroplated pads 51, in case the electroplated pads 51 cannot be firmly held by the encapsulant 54, this may similarly result in peel-off of the electroplated pads 51 due to the CTE mismatch between the semiconductor package and the printed circuit board, thereby seriously affecting the quality of the semiconductor package.
U.S. Pat. No. 6,770,959 has disclosed a semiconductor package shown in FIG. 3. In this semiconductor package, a lead layer 62 and a die pad layer 63 are firstly formed and defined by a solder mask layer 61. Then, a chip 64 is mounted on the die pad layer 63 and is electrically connected to corresponding positions of the lead layer 62 via a plurality of bonding wires 65. Subsequent conventional fabrication processes are performed to form an encapsulant 66 and complete the semiconductor package. This conventional packaging technology similarly encounters the above problem such as insufficient adhesion. Unlike the foregoing lead frame with stepped or anchoring structures, the encapsulant 66 and the lead layer 62 are still subject to delamination and cause cracks of the bonding wires 65.
Alternatively, another conventional packaging technology using a bumpless chip carrier has been proposed in U.S. Pat. No. 6,072,239. As shown in FIG. 4, a plurality of recessed electroplated pads 71 are formed on the chip carrier and are electrically connected to a chip 73 via a plurality of bonding wires 72, and an encapsulant 74 is used to encapsulate the chip 73 and the plurality of bonding wires 72 so as to fabricate a package structure. This packaging technology similarly incurs the problem that the recessed electroplated pads 71 and the encapsulant 74 are not well bonded to each other, which thus causes detachment of the bonding wires 72 and peel-off of the electroplated pads 71, and leads to the structural drawback of insufficient adhesion.
Therefore, the problem to be solved here is to provide a carrier-free semiconductor package and a fabrication method thereof, which can reduce the thickness of the semiconductor package, and assure the adhesion of an encapsulant, as well as protect the package structure and the electrical quality of bonding wires.